Graph analysis capability improving method based on planar fully-depleted silicon-on-insulator device

The invention relates to the field of integrated circuit design, in particular to a graph analysis capability improving method based on a planar fully-depleted silicon-on-insulator device, which comprises the following steps of: acquiring data of a main graph on an integrated circuit; inserting a virtual graph according to the data; according to a preset rule, screening out graphs which are easy to generate fillets; inserting scattering strips into at least part of corners of the screening pattern; inserting scattering strips according to the data; and executing optical proximity effect correction. According to the invention, the scattering strips are inserted into the corners of the graph which is easy to generate the filleted corners, so that the filleted corners of the graph are greatly reduced, the resolution ratio of the main graph and the graph analysis capability are improved, and the yield of products is improved. 本申请涉及集成电路设计领域，具体涉及一种基于平面型全耗尽绝缘体上硅器件的图形解析能力的提升方法，包括以下步骤：获取集成电路上主图形的数据；根据所述数据插入虚拟图形；根据预定的规