Integrated circuit device and method of forming same
A transistor includes a gate structure having a first gate dielectric layer and a second gate dielectric layer. A first gate dielectric layer is disposed over the substrate. The first gate dielectric layer includes a dielectric material of a first type having a first dielectric constant. A second ga...
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creator | YOU GUOFENG YANG FENGCHENG CHEN JIAWEI LIN SHIHAO CHEN HUIQI LIANG YUJIA LIN KUILUN LIAO SHANMEI XU ZHIYU CHEN YANMING CHEN JIANHAO |
description | A transistor includes a gate structure having a first gate dielectric layer and a second gate dielectric layer. A first gate dielectric layer is disposed over the substrate. The first gate dielectric layer includes a dielectric material of a first type having a first dielectric constant. A second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer includes a dielectric material of a second type having a second dielectric constant. The second permittivity is greater than the first permittivity. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.
一种晶体管包括具有第一栅极介电层和第二栅极介电层的栅极结构。第一栅极介电层设置在衬底上方。第一栅极介电层包含具有第一介电常数的第一类型的介电材料。第二栅极介电层设置在第一栅极介电层上方。第二栅极介电层包含具有第二介电常数的第二类型的介电材料。第二介电常数大于第一介电常数。第一介电常数和第二介电常数各自大于氧化硅的介电常数。本发明的实施例还涉及半导体器件及其形成方法。 |
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一种晶体管包括具有第一栅极介电层和第二栅极介电层的栅极结构。第一栅极介电层设置在衬底上方。第一栅极介电层包含具有第一介电常数的第一类型的介电材料。第二栅极介电层设置在第一栅极介电层上方。第二栅极介电层包含具有第二介电常数的第二类型的介电材料。第二介电常数大于第一介电常数。第一介电常数和第二介电常数各自大于氧化硅的介电常数。本发明的实施例还涉及半导体器件及其形成方法。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210629&DB=EPODOC&CC=CN&NR=113053882A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210629&DB=EPODOC&CC=CN&NR=113053882A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YOU GUOFENG</creatorcontrib><creatorcontrib>YANG FENGCHENG</creatorcontrib><creatorcontrib>CHEN JIAWEI</creatorcontrib><creatorcontrib>LIN SHIHAO</creatorcontrib><creatorcontrib>CHEN HUIQI</creatorcontrib><creatorcontrib>LIANG YUJIA</creatorcontrib><creatorcontrib>LIN KUILUN</creatorcontrib><creatorcontrib>LIAO SHANMEI</creatorcontrib><creatorcontrib>XU ZHIYU</creatorcontrib><creatorcontrib>CHEN YANMING</creatorcontrib><creatorcontrib>CHEN JIANHAO</creatorcontrib><title>Integrated circuit device and method of forming same</title><description>A transistor includes a gate structure having a first gate dielectric layer and a second gate dielectric layer. A first gate dielectric layer is disposed over the substrate. The first gate dielectric layer includes a dielectric material of a first type having a first dielectric constant. A second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer includes a dielectric material of a second type having a second dielectric constant. The second permittivity is greater than the first permittivity. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.
一种晶体管包括具有第一栅极介电层和第二栅极介电层的栅极结构。第一栅极介电层设置在衬底上方。第一栅极介电层包含具有第一介电常数的第一类型的介电材料。第二栅极介电层设置在第一栅极介电层上方。第二栅极介电层包含具有第二介电常数的第二类型的介电材料。第二介电常数大于第一介电常数。第一介电常数和第二介电常数各自大于氧化硅的介电常数。本发明的实施例还涉及半导体器件及其形成方法。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDxzCtJTS9KLElNUUjOLEouzSxRSEkty0xOVUjMS1HITS3JyE9RyE9TSMsvys3MS1coTsxN5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hobGBqbGFhZGjsbEqAEAGREshA</recordid><startdate>20210629</startdate><enddate>20210629</enddate><creator>YOU GUOFENG</creator><creator>YANG FENGCHENG</creator><creator>CHEN JIAWEI</creator><creator>LIN SHIHAO</creator><creator>CHEN HUIQI</creator><creator>LIANG YUJIA</creator><creator>LIN KUILUN</creator><creator>LIAO SHANMEI</creator><creator>XU ZHIYU</creator><creator>CHEN YANMING</creator><creator>CHEN JIANHAO</creator><scope>EVB</scope></search><sort><creationdate>20210629</creationdate><title>Integrated circuit device and method of forming same</title><author>YOU GUOFENG ; YANG FENGCHENG ; CHEN JIAWEI ; LIN SHIHAO ; CHEN HUIQI ; LIANG YUJIA ; LIN KUILUN ; LIAO SHANMEI ; XU ZHIYU ; CHEN YANMING ; CHEN JIANHAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113053882A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YOU GUOFENG</creatorcontrib><creatorcontrib>YANG FENGCHENG</creatorcontrib><creatorcontrib>CHEN JIAWEI</creatorcontrib><creatorcontrib>LIN SHIHAO</creatorcontrib><creatorcontrib>CHEN HUIQI</creatorcontrib><creatorcontrib>LIANG YUJIA</creatorcontrib><creatorcontrib>LIN KUILUN</creatorcontrib><creatorcontrib>LIAO SHANMEI</creatorcontrib><creatorcontrib>XU ZHIYU</creatorcontrib><creatorcontrib>CHEN YANMING</creatorcontrib><creatorcontrib>CHEN JIANHAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YOU GUOFENG</au><au>YANG FENGCHENG</au><au>CHEN JIAWEI</au><au>LIN SHIHAO</au><au>CHEN HUIQI</au><au>LIANG YUJIA</au><au>LIN KUILUN</au><au>LIAO SHANMEI</au><au>XU ZHIYU</au><au>CHEN YANMING</au><au>CHEN JIANHAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit device and method of forming same</title><date>2021-06-29</date><risdate>2021</risdate><abstract>A transistor includes a gate structure having a first gate dielectric layer and a second gate dielectric layer. A first gate dielectric layer is disposed over the substrate. The first gate dielectric layer includes a dielectric material of a first type having a first dielectric constant. A second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer includes a dielectric material of a second type having a second dielectric constant. The second permittivity is greater than the first permittivity. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.
一种晶体管包括具有第一栅极介电层和第二栅极介电层的栅极结构。第一栅极介电层设置在衬底上方。第一栅极介电层包含具有第一介电常数的第一类型的介电材料。第二栅极介电层设置在第一栅极介电层上方。第二栅极介电层包含具有第二介电常数的第二类型的介电材料。第二介电常数大于第一介电常数。第一介电常数和第二介电常数各自大于氧化硅的介电常数。本发明的实施例还涉及半导体器件及其形成方法。</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Integrated circuit device and method of forming same |
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