D FLIP-FLOP CAPABLE OF PREVENTING META-STABILITY

A D flip-flop capable of preventing meta-stability comprises a potential control circuit (100) and, a first phase inverter (10), a first latch unit (20), a second phase inverter (30), and a second latch unit (40) that are sequentially coupled. The potential control circuit (100) is used to control, when an input end (A) and an output end (B) of the first latch unit (20) are at the same level, the input end (A) and the output end (B) of the first latch unit (20) to be at a low level and a high level, respectively, or to be at a high level and a low level, respectively. When the input end (A) and the output end (B) of the first latch unit (20) are at the same level, the potential control circuit (100) is used to forcibly control the input end (A) and the output end (B) of the first latch unit (20) to be at different levels, thereby breaking a deadlock state in which the input end (A) and the output end (B) of the first latch unit (20) are at the same level, and preventing meta-stability. 本申请公开了一种防止亚稳态的D触发器，包括电位