Semiconductor structure analysis method

The invention provides a semiconductor structure analysis method, which comprises the following steps: providing a substrate on an insulator, the substrate comprising an upper semiconductor layer, a lower semiconductor layer and an oxide layer located between the upper semiconductor layer and the lower semiconductor layer, wherein a test block is formed on the surface of the upper semiconductor layer; etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer; filling the etching groove with a conductive medium to form a conductive path; and analyzing the test block by using a secondary ion mass spectrometry method. In the configuration, the conductive medium is filled in the formed etching groove to form a conductive path so as to connect the upper semiconductor layer and the lower semiconductor layer, so that an electric field formed by a large number of positive charges enriched in the test block is eliminated, and secon