Design method of variable fractional delay filter with symmetric coefficients

The invention relates to a design method of variable fractional delay filter with symmetric coefficients, which is particularly suitable for the field of broadband phased array signal processing. Aiming at the defect of high resource consumption caused by high order of a filter when certain performance is realized by the existing design method, the invention provides a method for realizing a higher-order filter with the same performance but only needing a half coefficient, so that the resource consumption for realizing the filter is reduced, and the performance is improved. Due to the symmetrical application, the calculation complexity in the digital signal processing process is reduced to a great extent, and low-cost application is also realized. 本发明涉及一种系数对称的可变分数延迟滤波器设计方法，尤其适合用于宽带相控阵阵列信号处理领域。针对已有的设计方法在实现一定性能时滤波器阶数较高，从而导致资源消耗较高的缺点，本发明给出了性能相同但只需要一半系数实现更高阶数滤波器的方法，降低了实现该滤波器的资源消耗，提升了性能。这一对称性应用不仅很大程度减小了数字信号处理过程中的计算复杂性，也实现了低成本的应用。