PROCESSOR MEMORY ACCESS

The invention relates to an IT device comprising: a plurality of ALUs (9); a set of registers (11); a memory (13); a memory interface between the registers (11) and the memory (13); a control unit (5)controlling the ALUs (9), generating: at least one cycle i including both the implementation of at least one first calculation by an arithmetic logic unit (9) and the downloading of a first data set(AA4_7; BB4_7) from the memory (13) to at least one register (11); and at least one cycle iI, subsequent to the at least one cycle i, including the implementation of a second calculation by an arithmetic logic unit (9), for which second calculation part (A4; B4) at least of the first data set (AA4_7; BB4_7) forms at least one operand. 本发明涉及一种计算装置，其包括：多个ALU(9)；一组寄存器(11)；存储器(13)；存储器接口，其在所述寄存器(11)和所述存储器(13)之间；控制单元(5)，其通过生成以下各项来控制所述ALU(9)：至少一个循环i，其包含借助于算术逻辑单元(9)实施至少一个第一计算操作和从所述存储器(13)将第一数据集(AA4_7；BB4_7)下载到至少一个寄存器(11)；以及至少一个循环ii，其在所述至少一个循环i之后，包含借助于算术逻辑单元(9)实施第二计算操作，针对所述第二计算操作，所述第一数据集(AA4_7；BB4_7)的至少一部分(A4；B4)形成至少一个操作数。