Wafer-level chip packaging structure and packaging method
The invention provides a wafer level packaging structure and a packaging method. The packaging method comprises the following steps: providing a wafer to be packaged; preparing a conductive column; preparing a groove structure in the wafer to be packaged; forming a packaging layer and enabling the p...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | The invention provides a wafer level packaging structure and a packaging method. The packaging method comprises the following steps: providing a wafer to be packaged; preparing a conductive column; preparing a groove structure in the wafer to be packaged; forming a packaging layer and enabling the packaging layer to extend into the groove structure; preparing a lead-out welding pad; exposing the encapsulation layer formed in the groove structure; and performing cutting from the position corresponding to the groove structure. According to the wafer-level packaging method for cutting the wafer based on the groove structure, in fan-out type wafer-level packaging, chip protection, wafer breakage prevention, manufacturing procedure shortening, operation period reduction, product yield improvement and product cost reduction are facilitated, effective six-face packaging of the wafer-level chip is further achieved through the surface mounting layer, the chip is packaged in a better way, and the reliability of the pro |
---|