Method for fabricating integrated circuit

The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, thesource contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout. 一种用于制造集成电路的方法包括接收定义半导体结构的IC设计布局，半导体结构具有在第一方向上纵向延伸的通孔轨，并且通孔轨接触在垂直于第一方向的第二方向上纵向延伸的源极接点。方法还包括使用IC设计布局上的图案识别来识别通孔轨、源极接点、与源极接点相距一定距离