INSTRUCTION LENGTH DECODER SYSTEM AND METHOD

The invention discloses an instruction length decoder system and method. The system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of afirst ending byte for the first macroinstruction. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions. 本申请公开了指令长度解码器系统和方法。提供了一种系统，其包括指令缓冲器和指令长度解码器电路，指令缓冲器