Calibration of an interpolative divider using a virtual phase-locked loop

A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibrationsignal based on the digital phase error signal. 本发明公开了一种时钟发生器包括插值除法器，该插值除法器包括相位插值器和多模除法器。插值除法器被配置为基于时钟信号、控制码和相位插值器校准信号来生成输出时钟信号。时钟发生器包括校准电路，该校准电路被配置为基于时钟信号、输出时钟信号和相位插值器代码来生成相位插值器校准信号。校准电路包括锁相环，该锁相环被配置为基于参考时间戳信号以及基于时钟信号和输出时钟信号