Chip integrated packaging method and integrated packaging structure

The invention relates to the field of semiconductors, and particularly discloses a chip integrated packaging method, which comprises the steps of arranging chips, filling the arranged chips with a curing agent to form a curing layer, exposing chip electrodes and manufacturing a circuit layer. The chip packaging process and cost can be simplified, and the product yield is improved. A circuit layerpost-manufacturing method is adopted, and the electrodes are directly used as the connection points of the circuit layer, so that the problem of poor connection between the prefabricated circuit connection points and the electrodes due to too small electrodes can be effectively solved, and repair can be carried out when poor chip electrodes and poor contact between the circuit layer and the electrodes are found. 本发明涉及半导体领域，具体公开了一种芯片集成封装方法，该方法包括将芯片进行排列，对排列后的芯片填充固化剂形成固化层，露出芯片电极，制作电路层，本发明可以简化芯片封装工艺及成本，提高产品良率，本发明采用电路层后制作的方法，并且直接使用电极做为电路层的连接点，可以有效解决因为电极过小，预制电路连接点与电极连接不良问题，且在发现芯片电极不良，电路层与电极接触不良的时候可以进行返修。