Hardware implementations of quasi-cyclic syndrome decoder

The invention discloses devices, systems and methods for providing hardware implementations of a quasi-cyclic syndrome decoder. An example method of reducing the complexity of a decoder includes receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code; computing a plurality of syndromes based on the noisy codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address as a function of the first syndrome; reading, based on the memory cell address, a coset leader corresponding to the first syndrome; anddetermining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword. 本发明公开了一种用于提供准循环校正子解码器的硬件实施方案的装置、系统和方法。一种降低解码器的复杂度的示例方法包括：接收基于从准循环线性码生成的所传送的码字的噪声码字；基于噪声码字计算多个校正子；从多个校正子中选择第一校正子；根据第一校正子生成存储器单元地址；基于存储器单元地址，读取与第一校正子相对应的陪集首；并且基于噪声码字和陪集首确定所传送的码字的候选版本。