Multi-level cache receiving and forwarding method based on FPGA synchronous serial port

The invention discloses a multi-level cache receiving and forwarding method based on an FPGA synchronous serial port. Data flow rates of a sender and a receiver are balanced through first-level cache,judgment of cache capacity and identifiers, calculation and judgment of a checksum, optional second-level cache supplementary calculation, judgment of the checksum and final-level cache. According tothe invention, a multi-level cache structure is adopted, so that the data problems of wrong numbers, missing numbers, majority and the like in a synchronous serial port can be effectively solved, theproblem of mismatching of transmission rates of which the data sending rates are greater than the data receiving rates in a part of time periods is effectively solved, the data packet receiving density is high, and the storage resource utilization efficiency is high. 本发明公开了一种基于FPGA同步串口多级缓存接收转发方法，通过一级缓存并判断缓存容量、标识符、计算并判断校验和，可选二级缓存补充计算、判断校验和，末级缓存平衡发送方、接收方数据流速。本发明采用多级缓存结构，可以有效解决同步串口中错数，漏数，多数等数据问题，有效解决部分时间段内出现发送数据率大于接收数据率的传输速率不