ZUC encryption system IP core construction method based on FPGA

The invention provides a ZUC encryption system IP core construction method based on an FPGA, and the method employs ZUC as a key stream generation algorithm, employs the output of an improved Logisticchaotic system based on a one-dimensional discrete chaotic system as an initial vector IV of the ZUC, and employs a stream management mode to achieve the data interaction among all modules when the encryption system is achieved through hardware. In a transmission mode, both the upstream side and the downstream side have rights to stop the opposite side and respond to the stop initiated by the opposite side, correct handshake logic and continuity of data are guaranteed through transmission, and an FIFO memory is added in a corresponding module for caching, so that the latent period of divergence between the upstream side and the downstream side converges to 1, and the advantage of parallel work of the FPGA is truly exerted. Thus, the running speed of the whole encryption system is effectively increased. According