High-integration-level nano-wall structure SRAM and implementation method

The invention provides a high-integration-level nano-wall structure SRAM and an implementation method. Compared with a traditional MOSFET in a FINFET and a GAA, the grid electrode of the MOSFET does not need to completely surround a channel region, so that the integration density is greatly improved; one side wall is occupied by an NMOS transistor, and three side walls are occupied by PMOS transistors, so that the width-to-length ratio of the P transistor is three times that of the N transistor, and the chip area is greatly reduced; a large number of MOSFETs can be manufactured on the same nanometer wall, and the MOSFETs are isolated by insulators to form a sea-like structure. A six-transistor unit SRAM is formed by the MOSFETs, so that the integration level can be greatly improved. 本专利提出一种高集成度纳米墙结构SRAM及实现方法，相比传统在FINFET和GAA中的MOSFET而言，本专利中的MOSFET的栅极不必全包围沟道区，因此，集成密度大大提高；通过NMOS管占用1面侧墙，PMOS管占用3面侧墙来实现P管的宽长比为N管的宽长比的3倍，极大的减小了芯片面积；在同一面纳米墙上可以制做大量MOSFET，MOSFET间由绝缘体隔离，形成类似门海结构；由上述MOSFET构成六管单元SRAM，可大大提高集成度。