Full-pipelined multiply-add unit array circuit for convolutional neural network

The invention discloses a full-pipelined multiply-add unit array circuit for a convolutional neural network, which is characterized by comprising a plurality of multiply-add units where n multiply-addunits are arranged along a first direction and are connected together in a cascaded mode to form a multiply-add sub-module, m multiply-add sub-modules are arranged along a second direction to form amultiply-add core module, i multiply-add core modules are arranged along a third direction to form the array circuit comprising n * m * i multiply-add units, wherein m, n and i are integers not less than 2, and the first direction, the second direction and the third direction are different. The circuit provided by the invention can effectively improve the reuse rate of data, fully shortens the idle time of an operation unit, and improves the implementation efficiency of convolution operation hardware. 本发明公开了一种用于卷积神经网络的全流水线乘加单元阵列电路，其特征在于，包括多个乘加单元，所述多个乘加单元的排布方式为：单个乘加单元沿着第一方向重复排列n个，所述n个乘加单元通过级联的方式连接在一起形成乘加子模块；所述乘加子模块沿着第二方