SPLIT-GATE FLASH MEMORY CELL WITH IMPROVED READ PERFORMANCE

Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positiveor negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating the split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltageto the word line, applying a second non- zero voltage to the bit line, and applying a third non-zero voltage VCGR to the control gate. 本公开的实施方案提供了用于改善分裂栅闪存单元中的读取窗的系统和方法，例如，通过在单元读取操作期间用非零(正或负)电压偏压控制栅端子来改善或控制该单元的擦除状态读取性能或编程状态读取性能。操作分裂栅闪存单元的方法可以包括在该单元中执行编程操作、执行擦除操作和执行读取操作，其中每个读取操作包括向字线施加第一非零电压，向位线施加第二非零电压，以及向控制栅施加第三非零电压VCGR。