CLOCK SYNCHRONIZATION IN ADPLL

Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with aPFD operation. Other embodiments are also described. 公开了全数字锁相环(ADPLL)的时钟同步单元、ADPLL的逐次逼近寄存器(SAR)时间-数字转换器(TDC)以及ADPLL中的时钟同步方法的实施例。在一个实施例中，ADPLL的时钟同步单元包括双触发器同步器、连接到所述双触发器同步器的相位频率检测器(PFD)，以及同步控制电路，其被配置成控制所述双触发器同步器和所述PFD以执行参考时钟输入