FPGA layout method, device, electronic equipment and computer readable medium

The embodiment of the invention provides an FPGA layout method, a device, electronic equipment and a computer readable medium. The method comprises the steps: carrying out the initial layout of an FPGA according to a global layout algorithm, and obtaining an initial layout result; obtaining the time margin of each path, and taking the path of which the time margin is less than a time threshold asa first path; determining a first logic unit on the first path, and searching a second logic unit located on a second path according to the first logic unit; if a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit located on a third path; and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit onthe third path with the first logic unit. According to the invention, when the logic unit block exists between the first logic unit and the second logic unit, the circuit connection length is effectively shortened by obtainin