Data weighted average algorithm module and analog-to-digital conversion circuit

The invention discloses a data weighted average algorithm module and an analog-to-digital conversion circuit. The data weighted average algorithm module comprises no less than three groups of parallelstructures, and each parallel structure comprises a state machine unit, a logic comparator, a pointer generator and a trigger which are connected to form a loop body. The state machine unit is used for acquiring current state output information according to the feedback information of the trigger and the state output information of the state machine unit in the previous group of parallel structures; and the pointer generator is used for determining pointer output information according to a current logic comparison result and the logic comparison result output by the previous group of parallelstructure logic comparators so that a probability that each capacitor in an external high-order capacitor array is selected is the same. The module and the circuit have the characteristics of higherdata processing speed, simp