Frequency synthesizer output cycle period including ring encoder
The invention relates to a frequency synthesizer output period counter including a ring encoder. In described examples of a method of frequency estimation, a clock output from a frequency synthesizer(110) is received at an input of a ring encoder (121). The ring encoder (121) generates outputs, incl...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention relates to a frequency synthesizer output period counter including a ring encoder. In described examples of a method of frequency estimation, a clock output from a frequency synthesizer(110) is received at an input of a ring encoder (121). The ring encoder (121) generates outputs, including a ring encoder output clock and an encoded output that represents LSBs of a clock cycle countof the clock output. A binary counter (122) is run using the ring encoder output clock, which provides an output count that represents MSBs of the clock cycle count. A frequency estimator (123) thatis provided a reference clock is used, the encoded output is sampled to provide a sampled encoded output, and the output count is sampled to provide a sampled output count. Error correcting is appliedto the sampled encoded output to provide a corrected sampled encoded output, and the corrected sampled encoded output and sampled output count are combined, which is used for estimating an instantaneous or average frequency of |
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