INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS

The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays,a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first oneof the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device. 本公开包含一种用于具有高速缓冲存储器及多个独立阵列的存储器的接口。一实施例包含：存储器装置，其具有高速缓冲存储器及多个独立存储器阵列；控制器；及接口，其经配置以将多个命令从所述控制器传递到所述存储器装置，其中所述接口包含引脚，所述引脚经配置以在所述存储器装置接收到所述多个命令中的第一命令之后即刻激活，且一旦所述存储器装置已执行所有所述多个命令便撤销激活。