Dynamic phase-locked loop based on digital direct linear phase comparison

The invention discloses a dynamic phase-locked loop based on digital direct linear phase comparison. A frequency conversion circuit is connected with a voltage-controlled voltage oscillator VCXO aftersequentially passing through an ADC module, an FPGA module and a low-pass filter, and the frequency conversion circuit processes an input reference signal into a clock signal for controlling the conversion rate of the ADC module and sends the clock signal to the ADC module; the FPGA module receives the reference signals processed by the ADC module and outputs PWM waves to the low-pass filter, thelow-pass filter processes the PWM waves into corresponding direct-current voltage, and voltage-controlled voltage output of the voltage-controlled voltage oscillator VCXO is changed; the voltage-controlled voltage oscillator VCXO is subjected to linear transformation through the amplitude preprocessing circuit and then is sent to the ADC module; a dynamic phase-locked loop based on digital directlinear phase comparison is