FPGA-based two-dimensional ordered statistical constant false alarm detector implementation method

The invention relates to the technical field of radar target detection, and in particular, relates to an FPGA-based two-dimensional ordered statistical constant false alarm detector implementation method. According to the method disclosed by the invention, detection is carried out in each clock period from two-dimensional power matrix input, so that the repeated reading time delay of the data cache is reduced, and the detection speed can be effectively improved. Aiming at the condition of large calculated amount in a traditional OS-CFAR (Ordered Statistical Constant False Alarm Rate) sorting process, the FPGA implementation method is completed by adopting parallel comparison, so that the sorting complexity is reduced. The reusability of a module is fully considered, two-dimensional slidingwindow structure setting is completed through a shifting register set, two-dimensional OS-CFAR detection is achieved, and BRAM memory resources and DSP resources of the FPGA can be saved. 本发明雷达目标检测技术领域，具体涉及一种基于FPGA的二维有序统计恒虚警