Time sequence model, time sequence model establishing method and related top layer analysis method

The invention discloses a time sequence model, a time sequence model establishing method and a related top layer analysis method. The time sequence model includes an interface netlist and a specific internal netlist corresponding to a gate-level netlist. And if the gate-level netlist contains the unlimited clock rate tree and the boundary time sequence limitation information of the gate-level netlist does not contain the time sequence limitation of the unlimited clock rate tree, the interface netlist does not contain a circuit unit driven by the unlimited clock rate tree in the gate-level netlist. A particular internal netlist is cross-coupled to the interface netlist. According to the time sequence model, the accuracy of top analysis can be improved, and the time required by analysis canbe reduced. 一种时序模型、时序模型建立方法、与相关的顶层分析方法。时序模型包含对应于门级网表的接口网表和特定内部网表。若门级网表包含未限制时脉树，且门级网表的边界时序限制信息未包含未限制时脉树的时序限制，则接口网表不包含门级网表中由未限制时脉树驱动的电路单元。特定内部网表交叉耦合至接口网表。上述的时序模型能增进顶层分析的准确度并减少分析所需时间。