Porous Cu on Cu surface for semiconductor packages

A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallizedsurface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 [mu]m to 10 [mu]m. A method of manufacturing a metal surface with such micropores also is described. 本发明公开了一种半导体封装件，其包括多个金属引线和通过互连附接到多个金属引线的半导体管芯。多个金属引线的表面、半导体管芯的金属化表面和/或互连的表面包括Cu，并且具有在340至400W/mK范围内的热导率以及在80％至110％IACS范围内的电导率。包括Cu并且具有在340至400W/mK范围内的热导率以及在80％至110％IACS范围内的电导率的一个或多个所述表面还包括具有在1μm至10μm范围内的直径的微孔。还描述了一种制造具有这种微孔的金属表面的方法。