Semiconductor memory device, memory system, and defect detection method

The embodiments of the invention relate to a semiconductor memory device, a memory system, and a defect detection method. A semiconductor memory device includes: a first wiring and a second wiring; amemory transistor connected between the first and second wirings; a first selection transistor connected between the first wiring and the memory transistor; a second selection transistor connected between the second wiring and the memory transistor; a third wiring connected to the gate electrode of the first selection transistor; and a fourth wiring connected to the gate electrode of the second selection transistor.. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and ata fourth timing between t