Test structure and evaluation method for semiconductor photo overlay

The disclosure relates to a test structure and an evaluation method for semiconductor photo overlay. A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layerand between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to eachsecond conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure. 公开用于半导体光刻套准的测试结构和评估方法。所述方法使用包括传感器结构和通孔链结构的测