Output data delay control module circuit and display panel

The invention provides an output data delay control module circuit and a display panel. The output data delay control module circuit comprises a front-end enable signal pulling-up device, a clock signal buffer and a D trigger. According to the invention, the front-end enable signal heightening device is added; when a source control signal or an output data delay control enable signal is input, a pull-up enable signal can be output. Even if the source control signal is interfered or impacted by electrostatic discharge, the front-end enable signal pulling-up device can enable the high-potentialtime period of the output pulling-up enable signal to be overlapped with the high-potential time period of the source control signal and the output data delay control enable signal, so that the influence of the electrostatic discharge is avoided. 本发明提供一种输出数据延迟控制模块电路及显示面板。输出数据延迟控制模块电路包括前端使能信号拉高器、时钟信号缓冲器以及D触发器。本发明通过增加一前端使能信号拉高器，可实现在输入一源控制信号或一输出数据延迟控制使能信号时输出一拉高使能信号，即使所述源控制信号受到静电放电干扰或冲击后，所述前端使能信号拉高器也能将输出的拉高使能信号的高电位时段与所述源控制信号及