In-chip system integrated packaging structure, manufacturing method thereof and three-dimensional stacked device

The invention provides an in-chip system integrated packaging structure, a manufacturing method thereof and a three-dimensional stacked device, and the in-chip system integrated packaging structure comprises a substrate, a chip, a first electric connection structure and a second electric connection...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: XIAO ZHIYI, YANG XIAOBING, WANG JIAO, SONG KUNSHU, MA SHUYING
Format: Patent
Sprache:chi ; eng
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Beschreibung
Zusammenfassung:The invention provides an in-chip system integrated packaging structure, a manufacturing method thereof and a three-dimensional stacked device, and the in-chip system integrated packaging structure comprises a substrate, a chip, a first electric connection structure and a second electric connection structure. The substrate is provided with a front surface and a back surface, the front surface is provided with a groove and a via hole welding pad, and the back surface is provided with a conductive through hole extending to the front surface via hole welding pad; the chip is embedded into the groove in the front surface of the substrate, and the other surface of the chip is provided with a chip welding pad; the first electric connection structure is formed on the front surface of the substrate, the second electric connection structure is formed on the back surface of the substrate, the first electric connection structure is electrically connected with the via hole welding pad and the chipwelding pad, and the sec