Measurement, calibration and tuning of memory bus duty cycle

The subject of the present invention is measurement, calibration and tuning of a memory bus duty cycle. A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. The storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is inputted directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is inputted into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed. 本发明题为"存储器总线占空比的测量、校准和调谐"。本发明公开了一种用于动态监测、测量和调整操作存储设备的时钟