High-reliability image sensor wafer-level fan-out packaging structure and method

The invention provides a high-reliability image sensor wafer-level fan-out packaging structure and method. The high-reliability image sensor wafer-level fan-out packaging structure comprises a substrate, a CIS chip, and solder balls. A photosensitive area of the CIS chip is arranged facing one surface of the substrate and the CIS chip is connected with one surface of the substrate through an areaaround the photosensitive area, a gap at the welding position of the CIS chip and the substrate is sealed through a light shielding material, and a back surface and a side surface of the CIS chip aresubjected to integral plastic package through a plastic package layer; the solder balls are arranged on a surface of the plastic package layer, and an RDL layer of the substrate is fanned out to the surface of the plastic package layer through through holes formed in the plastic package layer and is connected with the solder balls. According to the high-reliability image sensor wafer-level fan-outpackaging structure, the p