Clock signal frequency multiplier circuit

A clock signal frequency multiplier circuit comprises N branches and N frequency multiplier circuits; the branches are the same in structure, and each branch comprises a buffer and a frequency doubling circuit coupled with the buffer, wherein the frequency doubling circuits are suitable for carrying out frequency doubling on input reference clock signals to obtain frequency doubling reference clock signals. The N frequency doubling circuits comprise N second calibration delay circuits which are coupled with the N frequency doubling circuits in a one-to-one correspondence manner, and the secondcalibration delay circuits are suitable for carrying out clock delay on input frequency doubling reference clock signals to obtain frequency doubling reference clock signals after clock delay; and anN-path phase combination circuit is suitable for carrying out phase combination on the frequency doubled reference clock signals output by the N second calibration delay circuits after the N clocks are delayed to obtain 2N fr