DMOS with optimized electrical characteristics and manufacturing method thereof
The invention discloses a DMOS with optimized electrical characteristics and a manufacturing method thereof. The method comprises the following steps: an epitaxial layer is manufactured on a substrate, and a withstand voltage ring region of a second conductivity type is manufactured on the epitaxial...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a DMOS with optimized electrical characteristics and a manufacturing method thereof. The method comprises the following steps: an epitaxial layer is manufactured on a substrate, and a withstand voltage ring region of a second conductivity type is manufactured on the epitaxial layer; the upper side of the epitaxial layer is etched to form an LTO trench, the LTO trench is filled with silicon dioxide, the width and depth of the LTO trench are changed, and electric field distribution and electrical parameters around the LTO trench area can be changed. According to the DMOS,on the premise that Rsp increase is small, BVDSS is greatly increased, capacitance parameters are reduced, the output characteristic of the DMOS is optimized, working losses are reduced, the DMOS iscompatible with an existing process platform, the process is easy to achieve, and a process window is enough.
本发明公开一种优化电特性的DMOS及其制造方法。该方法包括在衬底上制作外延层,在外延层上制作第二导电类型的耐压环区;在外延层上侧刻蚀形成LTO沟槽,向LTO沟槽内填满二氧化硅,改变LTO沟槽的宽度和深度,可以改变LTO沟槽区域周围的 |
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