FPGA parallel implementation method of PFA

The invention discloses an FPGA parallel implementation method applied to a polar coordinate format algorithm in an airborne SAR real-time processing system and solves defects that an existing signalprocessing platform is insufficient in processing capacity and low in imaging precision under the requirements of extremely low power consumption, light weight limitation and miniaturization. A PFA high-precision imaging algorithm is adopted, engineering improvement of the algorithm is carried out on the basis of the Chirp Scaling principle (PCS), distance direction interpolation can be equivalently realized through two FFT operations, calculation is greatly reduced, acceleration processing of a polar coordinate format algorithm is achieved efficiently in parallel in an FPGA chip, and algorithm execution efficiency and the processing speed of a real-time imaging system are improved. The method is applied to an airborne SAR real-time processing system, has the capacity of conducting continuous and stable high-resol