VISIBLE ALIGNMENT MARKERS/LANDMARKS FOR CAD-TO-SILICON BACKSIDE IMAGE ALIGNMENT

A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. Thepower rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7nm feature sizes. 金属氧化物半导体(MOS)集成电路(IC)具有多个不同单元尺寸的基准标准单元。不同单元尺寸不均等地被利用。多个基准标准单元被放置为具有从