一种抗EMI超结器件

本发明涉及一种抗EMI超结器件，属于功率半导体器件技术领域。本发明提出的一种抗EMI超结器件，通过在漂移区内引入高K介质材料柱，从而与纵向相邻的半导体衬底、多晶硅调控栅形成MIS电容，并使多晶硅调控栅与外部电压调控模块相连，在不影响器件耐压的前提下，通过调节多晶硅调控栅上的电位，就可以改变不同漏压下密勒电容Cgd的大小，使Cgd曲线尽可能在低漏压下减小，高漏压下增大，从而实现开关损耗和开关EMI噪声的双向优化。 The invention relates to an anti-EMI super junction device, and belongs to the technical field of power semiconductor devices. The invention provides an anti-EMI super junction device. A high-K dielectric material column is introduced into a drift region, therefore, the MIS capacitor is formed by the semiconductor substrate and the polysilicon regulation and control gate which are adjacent to eachother in the longitudinal direction. The polycrystalline silicon regulation and control gate is connected with an external voltage regulation and control module; on the premise of not influencing thewithstand voltage of the device, the magnitude of the Miller capacitance Cgd under different leakage voltages can be changed by adjusting the potential on the polysilicon regulation and control gate,so that the Cgd cu