Wafer-level package device having high-standoff peripheral solder bumps

A wafer-level package device and techniques for fabricating the device are described. The wafer-level package device includes a second integrated circuit chip electrically coupled to a base integratedcircuit chip, wherein the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes the base integrated circuit chip, multiple high-standoff peripheral pillarswith solder bumps, and the second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip and in the center of an array of high-standoff peripheral pillars with solder bumps. 本申请公开了晶片级封装器件及所述器件的制作技术，所述器件包括电连接至基础集成电路芯片的第二集成电路芯片，其中所述第二集成电路芯片在具有焊料凸块的多个高支护外围立柱之间被放置在所述基础集成电路芯片上并被连接到所述基础集成电路芯片。在复数个实现方式中，根据本申请的采用实例的技术的晶片级封装器件包括基础集成电路芯片，具有焊料凸块的多个高支护外围立柱，和第二集成电