Matrix feature decomposition method based on FPGA

A matrix characteristic decomposition method based on an FPGA comprises the following steps: S1, initializing d0 (k) and X0 (8, k), (k = 0-63), wherein X0 (8, k) is an instantaneous value 8 * 1 complex vector of 64 beat amplitude phase sampling of each channel, and d0 (k) is a column sum vector of an X0 matrix; s2, calculating a feature vector; and S3, generating a noise subspace. According to thematrix feature decomposition method based on FPGA design, a signal processing flow is designed in a targeted mode, and high-speed matrix feature decomposition operation is achieved; according to themethod, the matrix feature decomposition operation time of the specified dimension is effectively prolonged, the practicability and universality are high, and certain guiding significance is achievedfor later similar design. 一种基于FPGA的矩阵特征分解方法，包括以下步骤：步骤S1、初始化d0(k)和X0(8，k)，(k＝0～63)；X0(8，k)为各通道64拍幅相采样的瞬时值8*1复向量，d0(k)为X0矩阵的列和向量；步骤S2、计算特征矢量，步骤S3、生成噪声子空间。本发明的基于FPGA设计的一种矩阵特征分解方法，有针对性的设计了信号处理流程，实现了高速矩阵特征分解运算；本发明有效提升了指定维度的矩阵特征分解运算时