Method of applying interfering trigger device soft error on circuit power line
The invention relates to a method of applying an interfering trigger device soft error on a power line of a circuit including a latch device and a memory device. The method comprsies the steps that first, an output voltage (1) is connected between a power supply and the power line of the circuit, an...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention relates to a method of applying an interfering trigger device soft error on a power line of a circuit including a latch device and a memory device. The method comprsies the steps that first, an output voltage (1) is connected between a power supply and the power line of the circuit, and then another output voltage (2) which can be positive or negative is connected through a switchingcircuit; secondly, the output of a pulse generation circuit is used as a control signal of on and off of the switching circuit; thirdly, the output voltage (2) is changed into interference voltage with different amplitudes, adjustable period and pulse width and controllable generation mode by controlling the on-off time of the switching circuit; and fourthly, the interference voltage and the output voltage (1) are superposed, causing voltage fluctuation on the power line of the circuit, enabling the latch device and the storage device to be in an abnormal working state at a certain moment, and enabling the trigger de |
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