Clock generating device and clock generating method

The invention relates to a clock generation device and a clock generation method. The clock generating device comprises a divisor register, a reference clock generator, a first counter, a second counter and a delay adjusting circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first period number of the reference clock signal to generate a first count value, and outputs a first clock signal according to the first count value and the divisor. The second counter counts a second period number of the first clock signal to generate a second count value, and outputs a second clock signal according to the second count value and the coefficient value. The delay adjusting circuit determines whether to control the first counter to delay the output of the first clock signal according to the first clock signal. 本申请涉及时钟产生装置及时钟产生方法。时钟产生装置包含除数寄存器、参考时钟产生器、第一计数器、第二计数器及延迟调节电路。除数寄存器提供除数。参考时钟产生器输出参考时钟信号。第一计数器计数参考时钟信号的第一周期数量以产生第一计数值，并根据第一计数值与除