CLOCK GENERATION CIRCUIT AND CLOCK ADJUSTMENT METHOD THEREOF

A clock generation circuit and a clock adjustment method thereof are provided. The clock generation circuit includes a fixed clock source, a variable clock source, a timing adjustment circuit, and a pulse width signal generator. The fixed clock source generates a reference clock signal having a fixed frequency. The variable clock source receives a frequency setting signal to correspondingly generate an operational clock signal having a variable frequency. The timing adjustment circuit determines whether a frequency of the operation clock signal is N times of a target frequency according to thereference clock signal to set a frequency of the operation clock signal. The pulse width signal generator divides the operating clock signal to generate a pulse width modulation signal having the target frequency. 本发明提供了一种时脉产生电路及其时脉调整方法。时脉产生电路包括固定时脉源、可变时脉源、计时调整电路及脉宽信号产生器。固定时脉源产生具有固定频率的参考时脉信号。可变时脉源接收频率设定信号，以对应地产生具有可变频率的操作时脉信号。计时调整电路依据参考时脉信号判断操作时脉信号的频率是否为目标频率的N倍，以设定操作时脉信号的频率。脉宽信号产生器对操作时脉信号进行除频，以产生具有目标频率的脉宽调变信号。