Sequential logic safety detection method and device for low-speed synchronous serial bus

The embodiment of the invention provides a sequential logic safety detection method and device for a low-speed synchronous serial bus, which are used for solving the problem that sequential logic loopholes and even hardware Trojan horses possibly exist in a bus transceiver cannot be detected at present. The method comprises the following steps: coupling a simulated low-speed synchronous serial bustransceiver with a low-speed synchronous serial bus, and simulating communication of the low-speed synchronous serial bus to obtain all synchronous time sequence signals of bus communication; coupling the simulation low-speed synchronous serial bus transceiver with a bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver; and comparing all the synchronous time sequence signals of the bus communication with the synchronous time sequence signals of the bus transceiver, and if the received synchronous time sequence signals of the bus transceiver are abnormal instate, determining that th