Clock signal generator, time domain interleaved analog-to-digital converter and method

The present invention relates to a clock signal generator, a time domain interleaved analog-to-digital converter and a method, and discloses the linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR which outputs the multi-bit states based on a system clock signal (CLK0). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLK1 and CLK2), wherein the pulse rate of CLK1 is slower than that of the CLK0 and is greater than that of CLK2. In some embodiments, a first multi-phase pulse generator can generate N-phases of CLK1 based on the CLK1 and N-phases of CLK0, and a second multi-phase pulse generator can generate N-phases of CLK2 based on CLK2 and N-phases of CLK0. Furthermore, additional registers can optionally use the N-phases of CLK2 to further generate N sets of M-phases of the CLK2. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)) whichincorporates the LFSR-bas