Semiconductor package
The invention relates to a semiconductor package. The semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and havin...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | BAE SUNG HAWN KIM JUNG SOO HAN PYUNG HWA |
description | The invention relates to a semiconductor package. The semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the firstsurface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.
本发明涉及一种半导体封装件,所述半导体封装件包括:连接构件,具有彼此背对的第一表面和第二表面,并且包括第一重新分布层;半导体芯片,设置在所述连接构件的所述第一表面上,并且具有连接到所述第一重新分布层的连接焊盘;包封剂,设置在所述连接构件的所述第一表面上,并且包封所述半导体芯片;布线结构,连接 |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN110993586A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN110993586A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN110993586A3</originalsourceid><addsrcrecordid>eNrjZBANTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBVqXmpJfHOfoaGBpaWxqYWZo7GxKgBAIfwIVs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package</title><source>esp@cenet</source><creator>BAE SUNG HAWN ; KIM JUNG SOO ; HAN PYUNG HWA</creator><creatorcontrib>BAE SUNG HAWN ; KIM JUNG SOO ; HAN PYUNG HWA</creatorcontrib><description>The invention relates to a semiconductor package. The semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the firstsurface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.
本发明涉及一种半导体封装件,所述半导体封装件包括:连接构件,具有彼此背对的第一表面和第二表面,并且包括第一重新分布层;半导体芯片,设置在所述连接构件的所述第一表面上,并且具有连接到所述第一重新分布层的连接焊盘;包封剂,设置在所述连接构件的所述第一表面上,并且包封所述半导体芯片;布线结构,连接</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200410&DB=EPODOC&CC=CN&NR=110993586A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200410&DB=EPODOC&CC=CN&NR=110993586A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BAE SUNG HAWN</creatorcontrib><creatorcontrib>KIM JUNG SOO</creatorcontrib><creatorcontrib>HAN PYUNG HWA</creatorcontrib><title>Semiconductor package</title><description>The invention relates to a semiconductor package. The semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the firstsurface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.
本发明涉及一种半导体封装件,所述半导体封装件包括:连接构件,具有彼此背对的第一表面和第二表面,并且包括第一重新分布层;半导体芯片,设置在所述连接构件的所述第一表面上,并且具有连接到所述第一重新分布层的连接焊盘;包封剂,设置在所述连接构件的所述第一表面上,并且包封所述半导体芯片;布线结构,连接</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBVqXmpJfHOfoaGBpaWxqYWZo7GxKgBAIfwIVs</recordid><startdate>20200410</startdate><enddate>20200410</enddate><creator>BAE SUNG HAWN</creator><creator>KIM JUNG SOO</creator><creator>HAN PYUNG HWA</creator><scope>EVB</scope></search><sort><creationdate>20200410</creationdate><title>Semiconductor package</title><author>BAE SUNG HAWN ; KIM JUNG SOO ; HAN PYUNG HWA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN110993586A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BAE SUNG HAWN</creatorcontrib><creatorcontrib>KIM JUNG SOO</creatorcontrib><creatorcontrib>HAN PYUNG HWA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BAE SUNG HAWN</au><au>KIM JUNG SOO</au><au>HAN PYUNG HWA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package</title><date>2020-04-10</date><risdate>2020</risdate><abstract>The invention relates to a semiconductor package. The semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the firstsurface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.
本发明涉及一种半导体封装件,所述半导体封装件包括:连接构件,具有彼此背对的第一表面和第二表面,并且包括第一重新分布层;半导体芯片,设置在所述连接构件的所述第一表面上,并且具有连接到所述第一重新分布层的连接焊盘;包封剂,设置在所述连接构件的所述第一表面上,并且包封所述半导体芯片;布线结构,连接</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN110993586A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor package |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T13%3A01%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BAE%20SUNG%20HAWN&rft.date=2020-04-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN110993586A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |