Circuitry for high-bandwidth, low-latency machine learning

The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform theseoperations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication). 本公开一般涉及用于使用集成电路器件有效地执行与人工智能(AI)、机器学习(ML)和/或深度学习(DL)应用(例如，训练和/或干扰计算)相关联的操作的技术。更具体地，本公开涉及一种集成电路设计，其被实现为以低延迟和/或高带宽的数据来执行这些操作。例如，公开了实现为对输入有效地执行一个或多个算术运