System and method for verifying SOC chip

The invention discloses a system and method for verifying an SOC chip. The system comprises a test program, wherein the test program is used for loading a test program on the SOC chip to be tested fordetection; the SOC chip to be tested comprises a first processor serving as an A core and a second processor serving as a P core which are connected with each other; the second processor is connectedwith a modem; the first processor is used for controlling the second processor to start control over the modem; and the second processor is also connected with a clock generator, a reset generator, the first processor and other peripherals. In combination with other structures or methods, relatively complex data interaction and control of a UVM verification method for the SOC chip in the prior art are effectively avoided; and the simulation process is inconvenient to control, so that the usability is low, and complex application scenes cannot be verified, and system-level verification cannotbe upgraded, and some modul