Manufacturing process of low electromagnetic interference power device terminal structure

The invention provides a manufacturing process of a low electromagnetic interference power device terminal structure. The terminal structure manufactured by the process comprises a metallized drain electrode, a first conductive type semiconductor substrate and a first conductive type semiconductor epitaxial layer, a second conductive type semiconductor main junction, a second conductive type semiconductor equipotential ring, a first conductive type cut-off ring, a second conductive type semiconductor field limiting ring, a first dielectric layer, a second dielectric layer, a third dielectric layer, a conductive field plate, a resistor and a metallized source electrode which are stacked from bottom to top. In the invention, an HK dielectric layer can be introduced between the field limitingring and the field plate. An MIS capacitor structure is formed by the semiconductor field limiting ring, the HK dielectric layer and the field plate and is connected in series with an adjacent polycrystalline silicon resisto