Self-recovery anti-phase unit structure

The invention relates to a self-recovery anti-phase unit structure, comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor. The self-recovery anti-phase unit structure is capable of achieving the function of inversely outputting the input signal, and at the same time, when the output nodeOUT is subjected to single event upset, due to the feedback characteristics of the first PMOS transistor and the third NMOS transistor, the value of the output node OUT can be rapidly corrected, and the feedback mechanism is started only when the output node of the self-recovery inverting unit is interfered, so that the hardware and power consumption expenditure for constructing the latch module are further reduced. The self-recovery anti-phase unit structure can be widely applied to a latch construction structure, is used for realizing a single event upset resistance reinforcement function, and is suitable for the fi