Apparatus to synchronize clocks of configurable integrated circuit dies through an interconnect bridge

The invention discloses an apparatus to synchronize clocks of configurable integrated circuit dies through an interconnect bridge. An IC, operable at a first clock phase, includes first and second IOsand a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a thirdclock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer. 本发明公开了一种通过互连桥对可配置集成电路管芯的时钟进行同步的设备。能够在第一时钟相位进行操作的IC包括第一和第